CDCE706 Key Features
- High-Performance 3:6 PLL-Based Clock Synthesizer/Multiplier/Divider
- User-Programmable PLL Frequencies
- Easy In-Circuit Programming via SMBus Data Interface
- Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
- Clock Inputs Accept a Crystal, a Single-Ended LVCMOS, or a Differential Input Signal
- Accepts Crystal Frequencies From 8 MHz to 54 MHz
- Accepts LVCMOS or Differential Input Frequencies up to 200 MHz
- Two Programmable Control Inputs [S0/S1, A0/A1] for User-Defined Control Signals
- Six LVCMOS Outputs With Output Frequencies up to 300 MHz
- LVCMOS Outputs Can Be Programmed for plementary Signals